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description the allegro ? ACS764 fully integrated hall-effect current sensor ic is designed for applications that require digital current sensing and reporting through an i 2 c? bus. allegro factory programming of the offset and gain, including the temperature coefficients, stabilizes the offset and gain over the operating temperature range. this programming greatly reduces the device total error, typically less than 2% over the operating temperature range. a fast response digital fault output is also provided. both coarse sensitivity and fault level can be programmed via an i 2 c control register, and can be used for enhanced diagnostic functions. the integrated low resistance conductor eliminates the requirement for external shunt resistors and, by employing hall-effect sensing technology, eliminates the error associated with changing sense resistance due to temperature. the device allows 16 unique i 2 c bus addresses, selectable via external pins. the sensor ic gain can be selected by the user through the i 2 c bus. the device uses a bicmos process that allows a highly stable chopper-stabilized small signal amplifier design. the ACS764 is provided in a compact 24-pin qsop package (suffix lf). the leadframe is plated with 100% matte tin, which is compatible with standard lead (pb) free printed circuit board assembly processes. internally, the device is pb-free, except for flip-chip high-temperature pb-based solder balls, currently exempt from rohs. ACS764-ds features and benefits ? fully integrated current sensor ic in a compact qsop package eliminates the need for shunt resistors ? hall effect sensing technology eliminates the error associated with shunt resistor variation due to temperature ? high accuracy: typical error < 2% over operating temperature range ? fast response digital fault output with programmable level through i 2 c bus interface ? digital output through i 2 c interface with 9-bit a-to-d conversion for high resolution current measurement ? user-selectable decimation averaging of current output; up to 256 samples ? freeze pin for holding current measurement value while reading many sensors serially ? user-selectable (via i 2 c) coarse sensitivity and oc fault levels, for exceptional flexibility to meet application requirements fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor package: 24-pin qsop (suffix lf) typical application diagrams not to scale ACS764 continued on the next page? i p ACS764 (i 2 c slave) v cc +3.3 v c byp 0.1 f r pu v cc v a1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ip+ ip+ ip+ ip+ ip+ ip+ ip+ vcc sda scl gnd nc ip? ip? ip? ip? ip? ip? ip? a1 a0 fault freeze nc v cc v a0
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 2 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings characteristic symbol notes rating unit forward supply voltage v cc 7v forward f a u l t pin voltage v fault 24 v dc forward voltage (a0, a1, freeze pins) v fdcx 7v dc reverse voltage (vcc, a0, a1, f a u l t , freeze pins) v rdcx ?0.5 v operating ambient temperature t a x temperature range ?20 to 125 oc maximum junction temperature t j (max) 165 oc storage temperature t stg ?65 to 165 oc selection guide part number packing* operating ambient temperature,t a (c) optimized current sensing range (a) optimized nominal resolution (ma/lsb) ACS764xlftr-32au-t tape and reel, 2500 pieces/reel ?20 to 125 32 62.62 ACS764xlftr-16au-t tape and reel, 2500 pieces/reel ?20 to 125 16 31.31 *contact allegro ? for additional packing options. ? less than 0.5 m series resistance greatly reduces power dissipation and heat generation ? factory programmed temperature compensation stabilizes sensitivity and offset voltage throughout the operating temperature range ? 16 programmable i 2 c addresses ? unidirectional dc current sensing and reporting ? immunity to stray magnetic fields simplifies pcb layout features and benefits (continued) thermal characteristics characteristic symbol test conditions value unit steady state package thermal resistance r ja tested with 30 a dc current and based on ACS764 demo board in 1 cu. ft. of still air. please refer to product faqs page on allegro website for detailed information on ACS764 demo board. 27 oc/w
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 3 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional block diagram dynamic offset cancellation tuned filter digital controller temperature sensor sensitivity master current supply control offset control hall drive vcc gnd c bypass eeprom adc data averaging fault logic i 2 c interface sda freeze scl a0 a1 fault ip? ip+ por and reset to all subcircuits pin-out diagram terminal list table number name function 1 to 7 ip+ primary current path input terminals 8 vcc device power supply 9 sda i 2 c control: interface data signal input/output 10 scl i 2 c control: clock signal input/output 11 gnd device ground 12,13 nc no internal connection; connect to gnd for optimal esd performance 14 freeze digital output register freezing control input; pull-up to stop data register updating 15 f a u l t i p fault flag output; active low 16 a0 i 2 c control: address input 0 17 a1 i 2 c control: address input 1 18 to 24 ip? primary current path output terminals 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ip+ ip+ ip+ ip+ ip+ ip+ ip+ vcc sda scl gnd nc ip? ip? ip? ip? ip? ip? ip? a1 a0 fault freeze nc
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 4 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com operating characteristics 1 valid throughout an ambient temperature range of ?20c to 125c, c bypass = 0.1 f, v cc = 3.3 v, unless otherwise noted characteristics symbol test conditions min. typ. max. unit electrical characteristics supply voltage v cc 3.0 ? 3.6 v supply current i cc no load on sda and scl ? 9 14 ma power-on time t po t a = 25c; c bypass = open ? 64 ? s internal bandwidth bw i small signal ?3 db; t a = 25c ? 2 ? khz leadframe resistance r p ip+ to ip? through primary current path ? 0.5 ? m current sensing range selection current sensing range 2,3 csr [gain_range] = 10b ? 8 ? a [gain_range] = 11b ? 16 ? a [gain_range] = 00b ? 32 ? a [gain_range] = 01b ? 64 ? a nominal resolution 3 res [gain_range] = 10b ? 15.66 ? ma/lsb [gain_range] = 11b ? 31.31 ? ma/lsb [gain_range] = 00b ? 62.62 ? ma/lsb [gain_range] = 01b ? 125.24 ? ma/lsb output signal characteristics a-to-d conversion resolution res adc ?9?bit a-to-d conversion time t adc ? 375 n? s average quantity of data points included in moving average calculation 4 n [n7:n0]=[0000 0000] through [ 1111 1111] represents 1 data point through 256 data points 1 ? 256 data point analog noise i noise (rms)(a) t a = 25c ? 15 ? ma analog noise density i noise (den)(a) t a = 25c ? 0.27 ? ma/hz 1/2 a-to-d linear range 5 adc lin 15 ? 496 adc code digital noise i noise (rms)(d) t a = 25c ? i noise (rms)(a) / n 1/2 ?ma accuracy performance offset error err os gain_range set for optimized csr, adc code is within adc lin ; measured at 2 a; t a = 25c to 125c ?8 5 +8 lsb gain_range set for optimized csr; adc code is within adc lin ; measured at 2 a; t a = ?20c to 25c ?15 7 +15 lsb continued on the next page?
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 5 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com operating characteristics 1 (continued) valid throughout an ambient temperature range of ?20c to 125c, c bypass = 0.1 f, v cc = 3.3 v, unless otherwise noted characteristics symbol test conditions min. typ. max. unit accuracy performance (continued) resolution accuracy res acc gain_range set for optimized csr, adc code is within adc lin ; t a = 25c to 125c; measured at 0.94 csr ?2.5 1 +2.5 % gain_range set for optimized csr, adc code is within adc lin ; t a = ?20c to 25c; measured at 0.94 csr ?3.5 1.5 +3.5 % nonlinearity error err lin gain_range set for optimized csr, adc code is within adc lin ? 0.75 ? % total error err tot gain_range set for optimized csr; adc code is within adc lin ; current = 0.94 csr; t a = 25c to 125c ?2.5 1 +2.5 % gain_range set for optimized csr; adc code is within adc lin ; current = 0.94 csr; t a = ?20c to 25c ?3.5 2 +3.5 % lifetime drift characteristics resolution lifetime drift res drift ? 3.0 ? % total error lifetime drift err tot _ drift ?3? % overcurrent fault detection resolution/timing fault current maximum setpoint i fault(max) fault_level = 0000b ? 1.46 csr ? a fault current minimum setpoint i fault(min) fault_level = 1111b ? 0.5 csr ? a digital fault level resolution res fault ?4?bit fault level error 6 e fault(min) gain_range set for optimized csr; measured at fault_level = 0000b ?4 2.5 +4 % e fault(max) gain_range set for optimized csr; measured at fault_level = 1111b ?7? % pull up resistance at f a u l t pin r pu 10 ? ? k f a u l t output voltage v fault rpu = 10 k , under fault condition ? ? 0.4 v fault response time t fault delay from i p rising above i fault until v fault < 0.4 v ? 100 ? s freeze pin characteristics freeze pin input level (low) v freeze(il) ? ? 0.2 v cc v freeze pin input level (high) v freeze(ih) 0.8 v cc ??v freeze pin input impedance r freeze(in) ?10?k continued on the next page?
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 6 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com address pin characteristics 7 address value 0 voltage v addr0 a0, a1 pins ? 0 0.08 v cc v address value 1 voltage v addr1 a0, a1 pins 0.28 v cc 0.31 v cc 0.34 v cc v address value 2 voltage v addr2 a0, a1 pins 0.53 v cc 0.56 v cc 0.59 v cc v address value 3 voltage v addr3 a0, a1 pins 0.8 v cc v cc ?v input bias current i a0 a0 pin ? 100 ? na i a1 a1 pin ? 100 ? na 1 all current measurement accuracy specifications listed in this datasheet apply only for the optimized current sensing range. 2 the ACS764 will be most accurate in its optimized gain range. 3 the gain_range setting of 11b selects the optimized nominal resolution for the 16au variant, and the gain_range setting of 00b selects the optimized nominal resolution for the 32au variant. 4 programmable by user through the i 2 c interface. 5 the adc is most linear within adc lin , so code readings outside adc lin should not be used for precise measurement. 6 percentage of csr. see table 3 and definitions of accuracy characteristics section. 7 address pin characteristics are ensured by designed but are not factory tested. operating characteristics 1 (continued) valid throughout an ambient temperature range of ?20c to 125c, c bypass = 0.1 f, v cc = 3.3 v, unless otherwise noted characteristics symbol test conditions min. typ. max. unit
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 7 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com i 2 c interface characteristics* valid at an ambient temperature range of ?20c to 125c and v cc = 3.3 v; unless otherwise noted characteristics symbol test conditions min. typ. max. unit bus free time between stop and start t buf 1.3 ? ? s hold time start condition t hdsta 0.6 ? ? s setup time for repeated start condition t susta 0.6 ? ? s scl low time t low 1.3 ? ? s scl high time t high 0.6 ? ? s data setup time t sudat 100 ? ? ns data hold time t hddat 0 ? 900 ns setup time for stop condition t susto 0.6 ? ? s logic input low level (sda, scl pins) v il ?? 0.3v cc v logic input high level (sda, scl pins) v ih 0.7v cc ?? v logic input current i in vin = 0 v to v cc ? 1 ? 1 a output voltage (sda pin) v ol r pu = 1 k , c b = 100 pf ?? 0.2 v cc v logic input rise time (sda, scl pins) t r ?? 300 ns logic input fall time (sda, scl pins) t f ?? 300 ns sda output rise time t r r pu = 1 k , c b = 100 pf ?? 300 ns sda output fall time t f r pu = 1 k , c b = 100 pf ?? 300 ns clock frequency (scl pin) f clk ?? 400 khz sda and scl bus pull-up resistor r pu ? 1 ? k total capacitive load for each of sda and scl buses c b ?? 100 pf *i 2 c interface characteristics are ensured by designed but are not factory tested. sda scl t susta t hdsta t sudat t hddat t susto t buf t low t r t f t r t f t high i 2 c interface timing diagram
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 8 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the ACS764 is a fully integrated hall-effect based current sensor ic with a digital current output and an overcurrent fault output for current monitoring and reporting applications. the digital out- put can be read from the ACS764 by a master controller through the i 2 c interface. the i 2 c interface can also be used to control some features of the ACS764. sixteen device addresses are avail- able through two input pins (a0, a1), allowing multiple devices to be connected to the same i 2 c bus in the application. the output data that can be read from the ACS764 through the i 2 c interface includes the following: ? current amplitude (9 bits) ? unlatched overcurrent fault flag (1 bit) ? latched overcurrent fault flag (1 bit) ? unread new current data flag (1 bit) the control data that can be written to the ACS764 through i 2 c interface includes the following: ? current range selection (2 bits) ? overcurrent fault level selection (4 bits) ? digital averaging filter data point selection (8 bits) ? latched overcurrent fault flag reset (1 bit) i 2 c interface i 2 c is a serial interface that uses two bus lines, scl and sda, to access the internal device registers. data is exchanged between a master controller (for example, a microcontroller) and the ACS764 (slave). the clock input to scl is generated by the master, while the sda line functions as either an input or an open drain output, depending on the direction of the data transfer. the i 2 c input thresholds depend on the v cc voltage of the ACS764. timing considerations i 2 c communication is composed of several steps in the following sequence: 1. start condition. defined by a negative edge on the sda line, while scl is high. 2. address cycle. 7 device (slave) address bits, plus 1 bit to indicate write (0) or read (1), followed by an acknowl- edge bit. 3. data cycles. reading or writing 8 data bits, followed by an acknowledge bit. this cycle can be repeated for multiple bytes of data transfer. if there are multiple registers in a device (for example, eeprom), the first data byte could be the register address. see the following sections for further information. 4. stop condition. defined by a positive edge on the sda line, while scl is high. except to indicate a start or stop condition, sda must be stable while the clock is high. sda can only be changed while scl is low. it is possible for the start or stop condition to occur at any time during a data transfer. the ACS764 always responds by resetting the data transfer sequence. the state of the read/write bit is set low to indicate a write cycle and set high to indicate a read cycle. the master monitors for an acknowledge pulse to determine if the slave device is responding to the address byte sent to the ACS764. when the ACS764 decodes the 7-bit address field as a valid address, it responds by pulling sda low during the ninth clock cycle. during a data write from the master, the ACS764 pulls sda low during the clock cycle that follows the data byte, in order to indi- cate that the data has been successfully received. after sending either an address byte or a data byte, the master device must release the sda line before the ninth clock cycle, in order to allow the handshaking to occur. writing to ACS764 registers through the i 2 c interface bus the master controls the ACS764 by programming it as a slave. to do so, the master transmits data bits to the sda input of the ACS764 in synchronization with the clocking signal it transmits simultaneously on the scl input. a complete transmission begins with the master pulling sda low (start bit), and completes with the master releasing the sda line (stop bit). between these points, the master transmits a pattern of slave device (ACS764) address bits with a write command (d0 = 0), and then the target register address (within that device), application information
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 9 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com and finally the data for the register. each register in the ACS764 device is three bytes, or 24 bits, long. the address consists of two bytes, comprising: the ACS764 (device) address (7 bits) and the read/write bit, followed by the address byte of the individual register. the data stream of writing data to an individual register is shown in figure 1. after each byte, the slave ACS764 acknowledges by transmitting a low to the master on the sda line. after writing data to a reg- ister the master must provide a stop bit if writing is completed. if the stop bit is not set, then the next three bytes will be written to the current register address + 1. writing will continue in this fashion until the stop bit is received. if the total data byte count (that is, not including the register address byte) is not modulo three, then the write operation that would contain less than three bytes is not done. msb byte lsb byte register address ACS764 (slave) acknowledge ACS764 (slave) acknowledge ACS764 (slave) acknowledge ACS764 (slave) acknowledge ACS764 (slave) acknowledge master stop ACS764 bus address 123456789123456789 ak r7 ak r6 r5 r4 r3 r2 r1 r0 sda scl master start operation bit (write) a6 a5 a4 a3 a2 a1 a0 rw data byte 2 data byte 1 data byte 0 123456789123456789 ak ak 123456789 d7 ak d6 d5 d4 d3 d2 d1 d0 sda scl ... ... ... ... d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 figure 1. i 2 c interface typical data write to an individual register in the ACS764
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 10 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com reading from ACS764 registers through the i 2 c interface bus when the master controller performs a data read from an ACS764 internal register, a so-called combined data transmission format is used. the i 2 c master provides the start bit, the ACS764 device (slave) address, the read/write bit set to write (0), and then the ini- tial source register address. the master then issues another start bit (referred to as restart ) followed by the same slave address and the read/write bit set to read (1). the ACS764 then provides three bytes of read data, one byte at a time. the data stream of reading data from an individual register is shown in figure 2. after each byte of data received, the master acknowledges by transmitting a low to the slave on the sda line. after receiv- ing three bytes of data from a register, the master must provide a stop bit if reading is completed. if the stop bit is not set, then the next three bytes will be read from the initial register address + 1. reading will continue in this fashion until the stop bit is received. please note that the acknowledge bit immediately before the stop bit should be a non-acknowledge (ak = 1). msb byte lsb byte register address ACS764 (slave) acknowledge ACS764 (slave) acknowledge ACS764 (slave) acknowledge master acknowledge master acknowledge master non-acknowledge master stop ACS764 bus address 123456789123456789 ak r7 ak r6 r5 r4 r3 r2 r1 r0 sda scl master start operation bit (write) a6 a5 a4 a3 a2 a1 a0 rw ACS764 bus address 123456789 ak master restart operation bit (read) a6 a5 a4 a3 a2 a1 a0 rw data byte 2 data byte 1 data byte 0 123456789123456789 ak ak 123456789 d7 nak d6 d5 d4 d3 d2 d1 d0 sda scl ... ... ... ... d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 figure 2. i 2 c interface typical data read from an individual register in the ACS764
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 11 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ACS764 bus address byte definitions address bit a6 a5 a4 a3 a2 a1 a0 binary device address value 1 1 0 0/1 0/1 0/1 0/1 a0, a1 v cc v cc 0.56 v cc 0.31 v cc ACS764 43 k 24 k 30 k 0 v i 2 c interface v a0, v a1 figure 3. external equivalent circuit for i 2 c device address selection i 2 c device (slave) address coding the four lsbs of the device (slave) address (a3, a2, a1, and a0) can be set by applying different voltages to pins a0 and a1 as show in figure 3 and defined in table 1. note: different values for the three msbs of the address (a6, a5, and a4) are available for factory programming if a conflict with other units occurs in the application design. table 1. i 2 c device address coding (refer to figure 3) voltage on a1 pin, v a1 voltage on a0 pin, v a0 device address # decimal binary (a3, a2, a1,a0) 0 v 0 v 0 0000 0 v 0.31 v cc 1 0001 0 v 0.56 v cc 2 0010 0 v v cc 3 0011 0.31 v cc 0 v 4 0100 0.31 v cc 0.31 v cc 5 0101 0.31 v cc 0.56 v cc 6 0110 0.31 v cc v cc 7 0111 0.56 v cc 0 v 8 1000 0.56 v cc 0.31 v cc 9 1001 0.56 v cc 0.56 v cc 10 1010 0.56 v cc v cc 11 1011 v cc 0 v 12 1100 v cc 0.31 v cc 13 1101 v cc 0.56 v cc 14 1110 v cc v cc 15 1111
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 12 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table 2. user-accessible volatile memory registers data register i 2 c register address bits parameter name description 0x00 23:12 reserved read as all 0s 0x00 11 non-latched_fault_status non-latched fault bit (read only) 0x00 10 latched_fault_status latched fault bit; resets with 1 written to this bit (read/write) 0x00 9 sync sync (new data) bit; resets when this register is read (read only) 0x00 8:0 current current sensor output value (digital filter output) (read only) control registers i 2 c register address bits parameter name description default 0x02 7:0 avg_points number of averaging points (read/write) 0 0x04 1:0 gain_range current sensing range selection (read/write) 0 (32au version) 3 (16au version) 0x06 3:0 fault_level fault threshold selection (read/write) 0
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 13 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com volatile register bits (address: 0x00) reserved current latched_fault_status non-latched_fault_status sync volatile register bits (address: 0x02) reserved avg_points volatile register bits (address: 0x04) volatile register bits (address: 0x06) reserved reserved gain_range fault_level x x x x 0/1 0/1 0/1 d8 xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxg1g0 xxxxxxxx xxxxxxxx xxxxf3f2f1f0 n7 n6 n5 n4 n3 n2 n1 n0 user-accessible register bit descriptions
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 14 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com control registers on power-up the control registers will be loaded to their default values from the eeprom. the settings can be changed after powering on the device by overwriting the control registers through the i 2 c interface. however, the control registers will revert to their previous levels if the sensor ic is power cycled. contact your local sales representative if you need the default control register values to be factory-programmed differently. data registers the volatile register at 0x00 holds all the output data of the device. it includes nine bits of current measurement data and three flag bits: one bit for current output update (sync), one bit for latched overcurrent fault (latched_fault_status), and one bit for non-latched overcurrent fault (non-latched_ fault_status), in that order. after the current measurement data has been updated, sync is set. it will be reset when the data is read by a master controller through the i 2 c interface. when an overcurrent fault condition is detected, both the latched_fault_status and the non-latched_ fault_status bits will be set. the non-latched_ fault_status bit will be reset after the overcurrent condition is removed. however, the latched_fault_status bit will remain set until a 24-bit word in the format: xxxx xxxx xxxx x1xx xxxx xxxx is written to the register. working with internal device registers through i 2 c
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 15 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com setting the overcurrent fault threshold example: if the required overcurrent fault threshold is 88% of the csr , then the required fault_level values are: 0110 (level 6). table 3. i 2 c control: settings for overcurrrent fault threshold fault_level bits i fault f3 f2 f1 f0 level setting ( %csr ) 0000050 0001156 0010263 0011369 0100476 0101582 0110688 0111795 1 0 0 0 8 101 1 0 0 1 9 108 1 0 1 0 10 114 1 0 1 1 11 120 1 1 0 0 12 127 1 1 0 1 13 133 1 1 1 0 14 140 1 1 1 1 15 146 the overcurrent fault threshold, i fault , is determined by setting the four fault_level bits. the combined settings determine the threshold as a percentage of current sensing range, csr. the f a u l t pin will be pulled low when the current is above the programmed i_fault level. the f a u l t pin will be released when the current drops below the programmed i_fault level. the digital non-latched fault status bit will be 1 when the current is above i_fault and 0 when the current is below i_fault. the latched fault status bit will be 1 when the current is above i_fault and will only return to being 0 when the current is below i_fault and the bit is reset by writing a 1 to it.
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 16 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristic performance data data taken using the ACS764-32au accuracy data mean +3 sigma maximum limit -3 sigma minimum limit 65.50 65.00 64.50 64.00 63.50 63.00 62.50 62.00 61.50 61.00 60.50 60.00 5.00 4.00 3.00 2.00 1.00 0 -1.00 -2.00 -3.00 -4.00 -5.00 4.00 3.00 2.00 1.00 0 -1.00 -2.00 -3.00 -4.00 err os (lsb) err tot (%) sens (mv/a) e fault(min) (%) t a (c) t a (c) t a (c) t a (c) -40 100 120 140 40 60 0 -20 20 80 -40 100 120 140 40 60 0 -20 20 80 -40 100 120 140 40 60 0 -20 20 80 -40 100 120 140 40 60 0 -20 20 80 -40 100 120 140 40 60 0 -20 20 80 8.00 6.00 4.00 2.00 0 -2.00 -4.00 -6.00 -8.00 -10.00 -12.00 e fault(max) (%) t a (c) 02226283032 10 14 4 2 6 18 20 24 81216 8.00 6.00 4.00 2.00 0 -2.00 -4.00 -6.00 err tot (%) current (a) 20.00 15.00 10.00 5.00 0 -5.00 -10.00 -15.00 -20.00 offset error versus ambient temperature total error versus ambient temperature resolution versus ambient temperature fault minimum error versus ambient temperature fault maximum error versus ambient temperature total error versus current t a = 25c
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 17 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com mean +3 sigma maximum limit -3 sigma minimum limit 33.00 32.50 32.00 31.50 31.00 30.50 30.00 5.00 4.00 3.00 2.00 1.00 0 -1.00 -2.00 -3.00 -4.00 -5.00 4.00 3.00 2.00 1.00 0 -1.00 -2.00 -3.00 -4.00 err os (lsb) err tot (%) sens (mv/a) e fault(min) (%) t a (c) t a (c) t a (c) t a (c) -40 100 120 140 40 60 0 -20 20 80 -40 100 120 140 40 60 0 -20 20 80 -40 100 120 140 40 60 0 -20 20 80 -40 100 120 140 40 60 0 -20 20 80 -40 100 120 140 40 60 0 -20 20 80 10.00 8.00 6.00 4.00 2.00 0 -2.00 -4.00 -6.00 -8.00 -10.00 e fault(max) (%) t a (c) 01416 810 4 26 12 6.00 5.00 4.00 3.00 2.00 1.00 0 -1.00 -2.00 -3.00 -4.00 20.00 15.00 10.00 5.00 0 -5.00 -10.00 -15.00 -20.00 err tot (%) current (a) offset error versus ambient temperature total error versus ambient temperature resolution versus ambient temperature fault minimum error versus ambient temperature fault maximum error versus ambient temperature total error versus current t a = 25c characteristic performance data data taken using the ACS764-16au accuracy data
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 18 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com a-to-d linear range (adc lin ) the range of the adc over which the adc code is proportional to the current being sensed. one should consider the adc satu- rated outside this range. see figure 4. offset error (err os ) the offset of the adc code versus the measured current from the ideal of zero. see figure 4. this parameter is measured at 2 a, as the adc is below adc lin at zero current. the offset error is calculated as: = err os res 1 adc code at 2 a ? 2000 (ma) resolution accuracy (res acc ) the resolution of the sensor is given in ma/lsb, which is the inverse of the slope of the adc code versus the measured current (see figure 4). multiplying the adc code by the resolution yields the measured current. the resolution accuracy (res acc ) is how close the actual resolution is to the nominal resolution (res). the resolution accuracy is calculated as: = res acc res measured resolution ? res 100 (%) nonlinearity error (err lin ) the nonlinearity error is a measure of how linear the adc code versus measured current curve is. the nonlinearity is calcu- lated as: = err lin adc code (0.94 csr) ? err os adc code (0.5 csr) ? err os 0.94 0.5 100 (%) 1? total error (err tot ) the percentage difference between the current measurement from the sensor ic and the actual current being measured (i p ), relative to the actual current. this is equivalent to the percentage dif- ference between the ideal adc code and the actual adc code, relative to the ideal adc code: = err tot (i p ) adc ideal (i p ) ? adc(i p ) adc ideal (i p ) 100 (%) the total error incorporates all sources of error and is a function of the measured current ( i p ). at relatively high currents, err tot will be mostly due to the resolution accuracy, and at relatively low currents, err tot will be mostly due to the offset error. fault level error (e fault(min) , e fault(max) ) the fault level error is a measure of the accuracy of the overcurrent fault function. e fault(min) is e fault measured at fault_level = 0000b, and e fault(max) is e fault measured at fault_level = 1111b. the fault level error is calcu- lated as: = e fault (fault_level) fault trip current csr 100 (%) ? i fault_percent where i fault_percent is the ideal percentage of csr at which the overcurrent fault should trip, based on the fault_level set- tings as given in table 3. for example, if fault_level is set to 0000b, the ideal trip point is at 50% of csr. an e fault(min) specification of 4% means the actual trip point ia between 46% and 54% of csr. definitions of accuracy characteristics measured current (i p ) (a) adc code (lsb) csr 511 adc lin (max) adc lin (min) 0 ignore (consider saturated) ignore (consider saturated) o ? set error 2 1/resolu on ideal adc behavior actual adc behavior { { figure 4. a-to-d linear range
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 19 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com dynamic response characteristics power-on time (t po ): when the supply is ramped to its operating voltage, the device requires a finite time to power its internal components before responding to a magnetic field due to current flow through the sensor. power-on time, t po , is defined as the time it takes from when the supply voltage (v cc ) reaches its minimum specified voltage to when the value from the adc is valid, as well as the fault bits and fault output.
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 20 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com amp regulator clock/logic hall element tuned filter anti-aliasing lp filter concept of chopper stabilization technique chopper stabilization technique when using hall-effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the hall element. this voltage is disproportionally small relative to the offset that can be produced at the output of the hall sensor ic. this makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating temperature and voltage ranges. chopper stabilization is a unique approach used to minimize hall offset on the chip. allegro employs a pat- ented technique to remove key sources of the output drift induced by thermal and mechanical stresses. this offset reduction technique is based on a signal modulation-demodulation process. the unde- sired offset signal is separated from the magnetic field-induced sig- nal in the frequency domain, through modulation. the subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover its original spectrum at baseband, while the dc offset becomes a high-frequency signal. the magnetic-sourced signal then can pass through a low-pass filter, while the modulated dc offset is suppressed. in addition to the removal of the thermal and stress related offset, this novel technique also reduces the amount of thermal noise in the hall sen- sor ic while completely removing the modulated residue resulting from the chopper operation. the chopper stabilization technique uses a high-frequency sampling clock. for demodulation process, a sample-and-hold technique is used. this high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. this approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent hall output voltages and precise recoverability after temperature cycling. this technique is made possible through the use of a bicmos process, which allows the use of low-offset, low-noise amplifiers in com- bination with high-density logic integration and sample-and-hold circuits.
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 21 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lf, 24-pin qsop 0.635 bsc 0.25 0.15 0.25 max 1.75 max 8o 0o 1.27 0.41 0.25 bsc 1.04 ref 8.66 0.10 3.91 0.10 0.30 0.20 5.99 0.20 c 0.20 24x seating plane c 0.635 2.30 5.00 0.40 2 1 24 gauge plane seating plane a c c b a for reference only, not for tooling use (reference jedec mo-137 ae) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown b reference pad layout (reference ipc7351 sop63p600x175-24m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances terminal #1 mark area pcb layout reference view standard branding reference view n = device part number t = temperature code lf = (literal) package type a = amperage tlf-aaa lllllllllll nnnnnnnnnnnnn branded face branding scale and appearance at supplier discretion
fully integrated, hall-effect based current sensor ic with i 2 c digital output and low-resistance current conductor ACS764 22 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2010-2013, allegro microsystems, llc i 2 c? is a trademark of philips semiconductors. allegro microsystems, llc reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions a s may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of allegro?s product can reasonably be expected to cause bodily harm. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, llc assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com

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